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iScience. 2021 Dec 17; 24(12): 103491.
Published online 2021 Nov 22. doi:10.1016/j.isci.2021.103491
PMCID: PMC8668989
PMID: 34917894
Wanying Du,1,2 Xionghui Jia,1,2 Zhixuan Cheng,1,2 Wanjing Xu,1 Yanping Li,1 and Lun Dai1,2,3,4,∗
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- Supplementary Materials
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Summary
Two-dimensional (2D) semi-conductive transition metal dichalcogenides (TMDCs) have shown advantages for logic application. Complementary metal-oxide-semiconductor (CMOS) inverter is an important component in integrated circuits in view of low power consumption. So far, the performance of the reported TMDCs-based CMOS inverters is not satisfactory. Besides, most of the inverters were made of mechanically exfoliated materials, which hinders their reproducible production and large-scale integration in practical application. In this study, we demonstrate a practical approach to fabricate CMOS inverter arrays using large-area p-MoTe2 and n-MoS2, which are grown via chemical vapor deposition method. The current characteristics of the channel materials are balanced by atomic layer depositing Al2O3. Complete logic swing and clear dynamic switching behavior are observed in the inverters. Especially, ultra-low power consumption of ∼0.37 nW is achieved. Our work paves the way for the application of 2D TMDCs materials in large-scale low-power-consumption logic circuits.
Subject areas: Engineering, Nanomaterials, Devices
Graphical abstract
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Highlights
•
A practical approach to fabricate large-scale CMOS inverter arrays is demonstrated
•
A method to balance the current characteristics of the channel materials is developed
•
Complete logic swing and clear dynamic switching behavior are observed
•
Ultra-low power consumption of ∼0.37 nW is achieved
Engineering; Nanomaterials; Devices
Introduction
Over the years, two-dimensional (2D) materials such as graphene and transition metal dichalcogenides (TMDCs) have stimulated great research enthusiasm, owing to their unique electronic and optoelectronic properties and ultrathin geometry (Akinwande etal., 2019; Fiori etal., 2014; Liu etal., 2021). Graphene, with high conductivity and high carrier mobility, has been extensively studied (Castro Neto etal., 2009; Flory etal., 2020; Novoselov etal., 2005; Yu etal., 2013). However, because of its gapless nature, graphene is not a good channel material for field-effect transistor (FET), which requires efficient electrostatic control. Semi-conductive TMDCs, with larger bandgaps, surpass graphene in this aspect. Recently, n-channel metal-oxide-semiconductor inverters (Wang etal., 2019) and p-channel metal-oxide-semiconductor inverters (Zhang etal., 2019) based on TMDCs have been reported. Complementary metal-oxide-semiconductor (CMOS) inverter, composed of an n-channel and a p-channel FET, has advantage in reducing power consumption and therefore is an important component in integrated circuits. However, so far, the performance of the reported TMDCs-based CMOS inverters is not satisfactory. They suffered from high power consumption (Liu etal., 2019; Pu etal., 2016) or large leakage current (Lin etal., 2014). Besides, most of the CMOS inverters were made of mechanically exfoliated TMDCs (Cho etal., 2019; Jeon etal., 2015; Pezeshki etal., 2016), which hinders their reproducible production and large-scale integration in practical application. Recently, large-area growth in a cost-effective way has been realized for several TMDCs via chemical vapor deposition (CVD) method (Pu etal., 2016; Wang etal., 2019; Xu etal., 2019a). The as-grown MoTe2 (Xu etal., 2019b) and MoS2 (Wang etal., 2019) are p- and n-type, respectively. Moreover, it is demonstrated that atomic layer deposition (ALD) of Al2O3 under certain conditions can cause n-type doping to 2D materials, including graphene (Zheng etal., 2015), MoS2 (Li et al., 2017), and MoTe2 (Lim etal., 2017; Park etal., 2019).
In this study, we fabricate CMOS inverter arrays using large-area CVD-grown p-MoTe2 and n-MoS2. We have developed a method to balance the current characteristics of the channel materials. Complete logic swing is obtained in our inverters. High voltage gain (∼23, much larger than 1) and noise margins close to ideal values are obtained. Especially, ultra-low peak power consumption of ∼0.37 nW is achieved, which is among the lowest power consumption values reported so far for TMDCs-based CMOS inverters under similar measurement conditions (Cho etal., 2019; Jeon etal., 2015; Pezeshki etal., 2016). We also investigate the dynamic switching behavior of the CMOS inverters and observe satisfying rising time tr (several hundred microseconds) and falling time tf (several hundred microseconds). Our work paves the way for the application of 2D TMDCs materials in large-scale low-power-consumption logic circuits.
Results and discussions
Figures 1A−1E are the corresponding optical images after each fabrication step, illustrating the fabrication process of our CMOS inverter array and demonstrating the feasibility of the large-scale fabrication method. First, arrayed Ti/Au (10/50nm) electrodes were fabricated on a SiO2 (285nm)/p+-Si substrate as buried gates for both of MoTe2 and MoS2 FETs. Then a 20-nm-thick Al2O3 dielectric layer was deposited on the substrate via ALD method (Figure1A). Second, a CVD-grown MoTe2 film (see Method details) was transferred onto the Al2O3 layer from the growth substrate with the help of polymethyl methacrylate (PMMA) and deionized water, which avoids the common use of hydrofluoric acid (Pu etal., 2016; Xu etal., 2019b). The transferred MoTe2 film was patterned (see Method details) into rectangular sheets (outlined by the red dashed lines) over the buried gates (Figure1B). Third, pairs of Pd/Au (10/50nm) source and drain electrodes (Electrodes 1 and 2) were fabricated on the ends of each MoTe2 sheet. After that, a 3-nm-thick Al2O3 layer was deposited on the MoTe2 FET array to protect MoTe2 from subsequent steps (Figure1C). For fabricating the MoS2 FET array, pairs of Pd/Au (10/50nm) source and drain electrodes (Electrodes 3 and 4) were fabricated on the Al2O3 layer (Figure1D). Herein, Electrode 3 and Electrode 2 have an overlapping area in the vertical direction (outlined by the black dashed lines) for measurement purpose. Similarly, MoS2 channels (outlined by the blue dashed lines) were fabricated by transferring and patterning a CVD-grown MoS2 film (see Method details). Finally, a 5-nm-thick Al2O3 layer was deposited on the whole substrate (Figure1E), which caused an n-type doping effect on MoS2. Figure1F is the optical image of a single inverter in the CMOS inverter array. To construct a complete CMOS circuit, the buried Gate Electrode and Electrode 1 were connected to the input voltage (Vin) and supply voltage (Vdd), respectively. Electrodes 2 and 3 were connected to a digital oscilloscope by a tungsten needle for output voltage (Vout) extraction. Electrode 4 was grounded. The cross-sectional schematic of the device structure depicted in Figure1F is shown in Figure1G. The CMOS circuit diagram is shown in the inset of Figure3C. Notably, in this work, we fixed the MoS2 FETs' channel length (15μm) and changed the MoTe2 FETs' channel lengths to make their current characteristics balanced. The optical image of the CMOS inverter array is presented in FigureS1C.
Figure1
Optical images that illustrate the fabrication steps of the CMOS inverter array
(A) Arrayed Ti/Au (10/50nm) electrodes were fabricated on a SiO2/Si substrate as buried gates for both of MoTe2 and MoS2 FETs. Then a 20-nm-thick Al2O3 dielectric layer was deposited on the substrate via ALD.
(B) A CVD-grown MoTe2 film was transferred onto the Al2O3 layer and patterned into rectangular sheets (outlined by the red dashed lines) over the buried gates.
(C) Pairs of Pd/Au (10/50nm) source and drain electrodes (Electrodes 1 and 2 in (F)) were fabricated on the ends of each MoTe2 sheet. After that, a 3-nm-thick Al2O3 layer was deposited on the whole substrate to protect MoTe2 from subsequent steps.
(D) Pairs of Pd/Au (10/50nm) source and drain electrodes (Electrodes 3 and 4 in (F)) were fabricated on the Al2O3 layer. Herein, Electrode 3 and Electrode 2 have an overlapping area in the vertical direction (outlined by the black dashed lines) for measurement purpose.
(E) The MoS2 channels (outlined by the blue dashed lines) were fabricated by transferring and patterning a CVD-grown MoS2 film. Finally, a 5-nm-thick Al2O3 layer was deposited on the whole substrate, which caused an n-type doping effect on MoS2.
(F) The optical image of a single inverter in the CMOS inverter array. The red, blue, and black dashed lines outline the MoTe2 sheet, the MoS2 sheet, and the overlapping area of Electrodes 2 and 3, respectively. To construct a complete CMOS circuit, the buried Gate Electrode and Electrode 1 were connected to Vin and Vdd, respectively. Electrodes 2 and 3 were connected to a digital oscilloscope by a tungsten needle for Vout extraction. Electrode 4 was grounded.
(G) The cross-sectional schematic of the device structure depicted in (F).
Figure3
Static operation performance of the inverters (with MoTe2 channel length of 15μm)
(A) The transfer curves of the MoTe2 and MoS2 FETs in an inverter at |Vds|= 1 V.
(B) The output curves of the MoTe2 and MoS2 FETs in the inverter at various Vgs with a step of 1 V.
(C) The VTCs and voltage gain (−dVout/dVin) plots of the inverter at various Vdd. The solid and dashed lines correspond to the output voltage and gain, respectively. Inset: the CMOS circuit diagram. For each Vdd applied (from 1 to 4 V), the VTC presents complete logic swing, and the maximum voltage gain is bigger than 1. At Vdd of 4 V, a maximum voltage gain of ∼23 and good noise margins (NML ≈ 0.40 Vdd, NMH ≈ 0.44 Vdd, total noise margin ≈ 0.84 Vdd) are obtained.
(D) The power consumption (Vdd × Idd) characteristics of the inverter at various Vdd. At Vdd of 1 V, peak power consumption of as low as ∼2.3 nW is achieved.
(E) The VTCs and voltage gain plots of another inverter at various Vdd. The solid and dashed lines correspond to the output voltage and gain, respectively. For each Vdd applied (from 1 to 4 V), the VTC presents complete logic swing. At Vdd of 4 V, a maximum voltage gain of ∼9.5 and good noise margins (NML ≈ 0.36 Vdd, NMH ≈ 0.40 Vdd, total noise margin ≈ 0.76 Vdd) are obtained.
(F) The power consumption characteristics of the inverter corresponding to (E) at various Vdd. At Vdd of 1 V, ultra-low peak power consumption of ∼0.37 nW is achieved.
The MoTe2 films (FigureS1A) used in our devices are formed by seamlessly stitched single crystal MoTe2 domains (Xu etal., 2019a). Figure2A shows the Raman spectrum of an as-grown MoTe2 film, which presents the Raman characteristic peak of 2H-MoTe2 at ∼235cm−1 (Yamamoto etal., 2014). Figure2B shows the atomic force microscope (AFM) image of the MoTe2 and the surface height profile along the white dashedline. The MoTe2 is about 6nm thick, corresponding to 9-layer MoTe2 (Lin etal., 2014). The MoS2 films (FigureS1B) used in our devices are formed by single crystal MoS2 domains (see the inset of Figure2C). Figure2C shows the Raman spectrum of an as-grown MoS2 film, which presents Raman characteristic peaks of MoS2 at ∼386 and ∼404cm−1 (Li etal., 2012). The peak distance is ∼18cm−1, demonstrating the monolayer nature of the MoS2 (Li etal., 2012).
Figure2
Optical, Raman, and AFM characterizations of the as-grown MoTe2 and MoS2
(A) The Raman spectrum of the as-grown MoTe2 under 532 nm laser illumination, which is dominated by the Raman characteristic peak of 2H-MoTe2 at∼235cm−1.
(B) The AFM image of the MoTe2 film and the surface height profile along the white dashed line. The MoTe2 is about 6nm thick, corresponding to 9-layer MoTe2.
(C) The Raman spectrum of the as-grown MoS2 under 532 nm laser illumination, which includes the Raman characteristic peaks of MoS2 at ∼386 and∼404cm−1, with peak distance of ∼18cm−1, indicating the monolayer nature of the MoS2. Inset: the optical image of the MoS2 film. The MoS2 film is formed by single crystal MoS2 domains.
Figures 3A and 3B show the transfer curves and output curves of the MoTe2 FET (with 15μm channel length) and MoS2 FET in an inverter, respectively. The transfer curves are approximately symmetrical about theirintersection. Note that the two ALD steps in the device fabrication process balanced the carrier concentrations of the MoTe2 and MoS2, enabling the realization of high-performance CMOS inverters (FigureS2). It is worth noting that, in order to avoid the ALD-caused n-type doping effect on the p-MoTe2, we also fabricated a CMOS inverter array with another device structure, where the MoTe2 is free from Al2O3 coverage (FigureS4). The overall device performance did not improve (FigureS5). Figure3C shows the voltage transfer characteristics (VTCs) and voltage gain (−dVout/dVin) plots of the inverter corresponding to Figures 3A and 3B. The inset is the CMOS circuit diagram. For each Vdd applied (from 1 to 4 V), the VTC presents complete logic swing, and the maximum voltage gain is bigger than 1, satisfying the requirement for logic application. At Vdd of 4 V, a maximum voltage gain of ∼23 and good noise margins (NML ≈ 0.40 Vdd, NMH ≈ 0.44 Vdd, total noise margin ≈ 0.84 Vdd) are obtained, indicating the potential of the CMOS inverter to be integrated into complex circuit systems (Wang etal., 2019). The noise margins for high input voltage (NMH) and low input voltage (NML) are defined as NMH= VOH − VIH and NML= VIL – VOL. VOH and VOL are the highest and lowest output voltages, respectively. VIH and VIL are, respectively, the higher and lower input voltages, at which the voltage gains of the VTC equal 1. The total noise margin is the sum of NMH and NML. To evaluate the noise margins of our CMOS inverter, the input voltage range of the VTC is shifted to be symmetric with the output voltage range (Das etal., 2014). Figure3D shows the power consumption (Vdd × Idd) characteristics of the inverter. At Vdd of 1 V, peak power consumption of as low as ∼2.3 nW is achieved. Figures 3E and 3F show the VTCs and power consumption characteristics of another inverter (with MoTe2 channel length of 15μm). For each Vdd applied (from 1 to 4 V), the VTC also presents complete logic swing. At Vdd of 4 V, a voltage gain of ∼9.5 and good noise margins (NML ≈ 0.36 Vdd, NMH ≈ 0.40 Vdd, total noise margin ≈ 0.76 Vdd) are obtained. Especially, ultra-low peak power consumption of ∼0.37 nW is achieved at Vdd of 1 V. The statistical gain and power consumption data of the CMOS inverter array are presented in Figures S3A and S3B. It is worth noting that the peak power consumption (0.37–2.3 nW) of our inverters at Vdd of 1V is lower compared with previously reported CMOS inverters based on p-MoTe2 and n-MoS2 and among the lowest peak power consumption values reported so far for TMDCs-based CMOS inverters (see Table 1). Besides, all the inverters exhibit maximum voltage gains of >1 at each Vdd applied.
Table 1
Power consumption comparison of the CMOS inverters based on TMDCs
| Channel materials | Vdd (V) | Peak power consumption (nW) | Measurement environment | Reference |
|---|---|---|---|---|
| CVD p-MoTe2 and n-MoS2 | 1 | 0.37 | Dark Ambient | This work |
| Ex. p-MoTe2 and n-MoS2 | 0.25 1 | 0.4 3–4 | Dark Room temperature | Pezeshki etal. (2016) |
| Ex. p-MoTe2 and n-MoS2 | 1 | 4 | Dark Room temperature | Cho etal. (2019) |
| Ex. p-MoTe2 and n-MoS2 | 3 | 400 | Dark Ambient | Seo and Jin (2019) |
| Ex. p-WSe2 and n-MoS2 | 1 5 | 0.1–1 1–10 | Dark | Jeon etal. (2015) |
| Ex. p-WSe2 and n-MoS2 | 1 | 1× 103 | Dark Room temperature | Liu etal. (2019) |
| CVD p-WSe2 and n-MoS2 | 1 | 20 | N2 atmosphere Room temperature | Pu etal. (2016) |
| Ex. p-MoTe2 and n-MoTe2 (n-doped) | 1 | 5 | Dark Room temperature | Lim etal. (2017) |
| Ex. p-WSe2 and n-MoS2 | 1.1 | 0.2 | Under 10−5 bar | Wang et al., 2020 |
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Ex., mechanically exfoliated; CVD, CVD-grown.
We also investigated the dynamic switching behavior of the CMOS inverters. Figures 4A−4C show the time-dependent Vout of an inverter (with MoTe2 channel length of 10μm) at Vdd of 3 V, driven by square wave Vin with various frequencies. The high and low levels of the input square wave were 0 and −6 V, respectively. Logic switching behavior is clear at 100Hz and remains to be observed ata critical logic switching frequency of 1 kHz. The tr and tf are about 340 and 308μs, respectively, at 1 kHz, calculated at 10% and 90% (marked by the red dashed lines in Figure4B) of Vout amplitude. The RC delays mainly result from the overlap capacitance in the CMOS circuit (Pezeshki etal., 2016; Wang etal., 2019). At 1.4 kHz, the amplitude of Vout decreased to half (∼1.5 V) of Vdd, with tr (tf) of about 275μs (290μs). The statistical dynamic switching frequency data of the CMOS inverter array are presented in FigureS3C.
Figure4
Dynamic switching behavior of an inverter (with MoTe2 channel length of 10μm)
(A−C) Time-dependent Vout at Vdd of 3V driven by square wave Vin with various frequencies. The high and low levels of the input square wave were 0 and−6V, respectively. Logic switching behavior is clear at 100Hz and remains to be observed ata critical logic switching frequency of 1 kHz. The rising time (tr) and falling time (tf) are about 340 and 308μs, respectively, at 1 kHz, calculated at 10% and 90% (marked by the red dashed lines in (B)) of Vout amplitude. At 1.4 kHz, the amplitude of Vout decreased to half (∼1.5 V) of Vdd, with tr (tf) of about 275μs (290μs).
Conclusions
We have fabricated CMOS inverter arrays using large-area CVD-grown p-MoTe2 and n-MoS2. The current characteristics of the channel materials were balanced by atomic layer depositing Al2O3 under proper conditions. Complete logic swing and clear dynamic switching behavior are observed in the inverters. The inverters have overall high performance such as maximum voltage gains of >1 at each Vdd applied, low and even ultra-low peak power consumption (0.37–2.3 nW), and satisfying tr (tf) and working frequencies. Our low-power-consumption CMOS inverters, with the merits of reproducibility and large-scale integration, have promising applications in future 2D microelectronic systems.
Limitation of the study
In order to further improve the device performance, developing new methods to increase the grain size of the monolayer MoS2 is needed.
STAR★Methods
Key resources table
| REAGENT or RESOURCE | SOURCE | IDENTIFIER |
|---|---|---|
| Chemicals, peptides, and recombinant proteins | ||
| Tellurium | Zhongnuoxincai | CAS: 13494-80-9 |
| Solid PTAS | 2D Semiconductors | N/A |
| Molybdenum(VI) oxide | Ourchem | CAS: 1313-27-5 |
| Sulfur | Aladdin | CAS: 7704-34-9 |
| PMMA | AllRESIST | CAS: 9011-14-7 |
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Resource availability
Lead contact
Further information and requests for resources should be directed to and will be fulfilled by the lead contact, Lun Dai (lundai@pku.edu.cn).
Materials availability
This study did not generate new unique reagents.
Method details
CVD growth of large-area MoTe2 and MoS2
Large-area MoTe2 and MoS2 films were grown via CVD method. For MoTe2 growth, Mo films were deposited on SiO2 (285nm)/p+-Si substrates via magnetron sputtering. Then, the substrates were placed in a quartz boat containing Te powder. Molecular sieves were placed in the quartz boat between the substrates and the Te powder. After that, the quartz boat was pushed into the center heating zone of a quartz tube furnace with a tube diameter of 1 inch. After evacuating the quartz tube to an air pressure of less than 1 mTorr, high-purity Ar was let in at the maximum flow rate until the pressure reached atmospheric pressure. Next, the furnace was heated to 650°C in 30min and kept there for 180min. High-purity H2 and Ar were used as carrier gases, whose flow rates were 7 and 5 standard cubic centimeters per minute (sccm), respectively. After the growth, the furnace cooled to room temperature naturally. For MoS2 growth, SiO2 (285nm)/p+-Si substrates were processed with O2 plasma. After that, perylene-3,4,9,10-tetracarboxylic acid tetrapotassium salt (PTAS) was spin-coated on the substrates as seeding promoter. The substrates were placed in a quartz boat containing MoO3 powder. Another quartz boat with S power was pushed into the upstream heating zone of a 3-temperature-zone quartz tube furnace with a tube diameter of 2 inch. Then the quartz boat with growth substrates was pushed into the downstream heating zone of the furnace. The growth was performed at atmospheric pressure. High-purity Ar (15 sccm) was used as carrier gas. The upstream and downstream heating zones of the furnace were heated to 200°C and 650°C, respectively, in 40min, and kept there for 5min. Finally, the furnace cooled to room temperature naturally.
Fabrication of the CMOS inverter arrays
Both the CVD-grown MoTe2 and MoS2 films were transferred with the help of PMMA and deionized water (Kim etal., 2019), and patterned into rectangular sheets through ultra-violet (UV) lithography and reactive ion etching. The Ti/Au and Pd/Au electrodes were fabricated via UV lithography, electron beam evaporation, and lift-off process. The Al2O3 layers were deposited using an ALD system (Cambridge NanoTech Inc., Savannah-100). The patterned Al2O3 layer (see FigureS4F) was fabricated via UV lithography, ALD, and lift-off process. In the ALD process, trimethylaluminum and deionized water served as precursors and high-purity N2 served as carrier gas. The reaction temperatures were 200°C for Al2O3 films covering the whole substrate and 80°C for the patterned Al2O3 layer (because the photoresist could not endure the temperature of 200°C). The Al2O3 thickness was controlled by deposition time.
Characterizations
The optical images of the devices were taken by an optical microscope (ZEISS, Axio Imager A2m). The Raman spectra were collected by a micro-zone confocal Raman system (WITec alpha 300R) under 532nm laser illumination. The thickness of the MoTe2 film was measured by an atomic force microscope (Asylum Research, Cypher S). All the electrical measurement was conducted in the dark with a semiconductor characterization system (Keithley 4200-SCS) that was connected to a probe station. For the dynamic switching performance measurement, a function generator (Tektronix AFG 3102) and a digital oscilloscope (Tektronix DPO 2024) were employed to generate the Vin and record the Vout, respectively. Both the function generator and the digital oscilloscope had common ground with the semiconductor characterization system, which provided the Vdd. All the characterizations were performed in ambient condition.
Acknowledgments
This work was supported by National Natural Science Foundation of China (Nos. 61521004, 61874003, and 62174005).
Author contributions
L.D. and W.Y.D. conceived the project. W.Y.D. grew the MoS2 and MoTe2 films, fabricated the devices, and conducted the measurement. L.D. and W.Y.D. performed data analysis. X.H.J. helped with the drawing of the cross-sectional schematics of the devices. Z.X.C. and X.H.J. helped with the design of the device structure. W.J.X. prepared the Mo films for MoTe2 growth. Y.P.L. helped with the deposition of the metal electrodes. L.D. supervised this research. W.Y.D. and L.D. wrote the manuscript. All authors contributed to discussions.
Declaration of interests
The authors declare no competing interests.
Notes
Published: December 17, 2021
Footnotes
Supplemental information can be found online at https://doi.org/10.1016/j.isci.2021.103491.
Supplemental information
Document S1. Figures S1–S5:
Click here to view.(1.4M, pdf)
Data and code availability
All data reported in this paper will be shared by the lead contact upon request.
This paper does not report original code.
Any additional information required to reanalyze the data reported in this paper is available from the lead contact upon request.
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